Programmable Video Processor with Fast Interrupt Response for MPEG Decoder
首发时间:2006-11-24
Abstract:An efficient programmable video processor based on the minimips together with fast interrupt response scheme designed to be used for the MPEG decoder is presented in this paper. The overall architecture, as well as the design for the fast interrupt response and exception handling, is discussed. A shadow register and hierarchical interrupt scheme approach is used. An external interrupt controller is developed, and the system is simulated.
keywords: MIPS, Processor, Interrupt.
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Programmable Video Processor with Fast Interrupt Response for MPEG Decoder
摘要:An efficient programmable video processor based on the minimips together with fast interrupt response scheme designed to be used for the MPEG decoder is presented in this paper. The overall architecture, as well as the design for the fast interrupt response and exception handling, is discussed. A shadow register and hierarchical interrupt scheme approach is used. An external interrupt controller is developed, and the system is simulated.
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No.9860901361164342****
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Programmable Video Processor with Fast Interrupt Response for MPEG Decoder
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