An process improvement recipe for gate oxide of high-voltage MOS devices

• 1、SHANGHAI JIAO TONG UNIVERSITY

Abstract：In the high-level geometry of VLSI below 0.25um technic, it is usually used in the process of the formation of STI (Shallow Trench Isolation) etching mode to achieve the purpose of isolated components. Due to the limited ability to process, the speed of oxidation rate at the corner of STI is different from the one over flat Si substrate, the thickness and smoothness at the corner of STI of MOS device is more difficult to control. It directly influences the reliability of the gate oxide layer. Seriously, the TDDB (Time Dependent Dielectric Breakdown) test is hard to get good data.. This subject mainly introduce something shown below. When doing the reliability analysis for EPFLASH (Embedded P-Channel Flash) 0.18um CMOS（Complementary Metal Oxide Semiconductor） technology product, based on process gate oxide VBD (Voltage to Breakdown) reliability uniformity problem of analysis, find out the key chain of the process, carry out and monitor several testing under a series of different test conditions. With the support which is from engineering experimental data obtained under the combination of several conditions, we got the conclusion that it is very important to have a control of the STI height after CMP (Chemical Mechanical Planarization) procedure. Finally this subject provides a gate oxide process improvement recipe of high-voltage MOS device. The implementation of the recipe can effecticely improve the product yield. This recipe is mainly about that: through the QA in-line SPC （Statistical Process Control） control of STI height after CMP procedure, we can ensure the oxide thickness and smoothness at the STI corner to reach the pre-specified criteria, thus ensuring the VBD uniformity of products. At the same time it makes sure the result in TDDB test reaches production criteria.

Keywords： Gate Oxide HV MOS Device Reliability Process Improvement