应用于手机DDR控制芯片的延迟锁相环设计
首发时间:2010-04-14
摘要:本文设计了一种采用0.18um CMOS工艺,工作电压为1.8V,应用于手机DDR 控制芯片端的延迟锁相环(Delay lock loop,DLL),对controller端延迟锁相环的工作原理和要求进行了深入了解,并在传统DLL电路结构的基础上,优化了鉴相器和压控延迟线的线路与设计参数,把压控延迟线的延迟控制在180°到540°之间,最终使得系统稳定工作在相位锁定的状况,结果表明,在DDR200的应用中,延迟能达到设计需求的0.25T,而且稳定。
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AN ANALOG DLL APPLIED IN MOBILE DDR
Abstract:In this paper, we designed a working in 1.8V, 0.18um CMOS technique analog delay lock loop, which is applied to mobile DDR controller. Based on the widespread investigation of DDR DLL working principle and existing DLL technological achievements, we optimization the delay line circuit. After simulate the final circuit, we achieve the DLL design, and meet the 25% T delay requirement.
Keywords: Mobile DDR Dealy lock loop
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No.4190349538112712****
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