SOI线性掺杂LDMOS的设计与实验
首发时间:2010-08-17
摘要:SOI LDMOS是通过将电压降转嫁到漂移区上来实现耐高压的。在实际工程应用中,我们考虑的是如何用最简单的工艺流程,得到尽可能高的击穿电压。本文根据已有的多种漂移区RESURF结构研究成果,用工艺模拟软件在3.5um外延厚度的SOI硅片上设计了一个简单的SOI线性掺杂LDMOS模型,并成功流片出耐压305V的SOI横向高压器件。
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Development of SOI LDMOS with Linearly Doped Drift Region
Abstract:The mechanism of high voltage SOI LDMOS is force potential drop on drift region. A lot of studies have been done on RESURF structure for drift region to compromise between the breakdown voltage and low switching-on resistance. However in engineering, more efforts have been spent on studying how to get higher breakdown voltage with lower cost processes. With 3.5um SOI wafer as substrate, we design an SOI LDMOS device with linear doping region. Its field distribution and breakdown voltage were simulated by Sentaurus. The SOI LDMOS was fabricated by standard 0.35um BICMOS process and tested. Results show that the SOI LDMOS structure has 305V breakdown voltage.
Keywords: SOI RESURF Linear doping drift region
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