一种基于65nm CMOS工艺的27.8KS/s, 0.35V,10位逐次逼近A/D转换器
首发时间:2013-12-11
摘要:设计实现了一款10位27.8KS/s 0.35V超低功耗逐次逼近型(SAR ) A/D转换器。提出了一种分段的三基准电容开关时序,有效地减小了电容D/A转换器的功耗,使转换器功耗在纳瓦数量级。为了避免偏置电路引入额外功耗,设计采用了全动态比较器。提出了一种基于动态锁存结构的逻辑单元以消除因漏电导致的误码。在D/A转换器的电容阵列中使用了升压技术减小非线性误差。使用一种新型的两倍自举的采样开关以减小漏电并提高线性度。整个转换器基于65nm CMOS工艺实现,测试结果显示,SAR A/D转换器在0.35V电源电压,27.8KS/s采样速率时,功耗为25.2nW,信噪失真比为54.57dB,低速输入是的有效位数为8.77位,优值为2.08fJ/conversion-step。
关键词: 微电子学与固体电子学 模数转换器 开关时序 低功耗 动态逻辑
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A 27.8kS/s 0.35V 10-bit successive approximation register ADC in 65nm CMOS
Abstract:A 10-bit 27.8KS/s 0.35V ultra low power SAR analog-to-digital converter (ADC) is presented. Nano-watt range power consumption is achieved thanks to the proposed split capacitor array structure and ultra low voltage design. The fully comparator is used to avoid the need of the extra biasing circuits. A novel latched dynamic logic cell is introduced to eliminate decision error caused by leakage current. Boosting technique is introduced in DAC driving switch to relieve nonlinearity. A new double-boosted sample switch is employed to reduce leakage current and improve sampling linearity. The ADC was fabricated in 65nm CMOS. Drawing 25.2nW from a single 350mV supply, the ADC achieves 54.57dB SNDR and 8.77bit ENOB resulting in a figure-of-merit (FOM) of 2.08fJ/conversion-step.
Keywords: Microelectronics and Solid-State Electronics Analog-to-digital converter, Capacitor switching procedure, Low power, Dynamic logic
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一种基于65nm CMOS工艺的27.8KS/s, 0.35V,10位逐次逼近A/D转换器
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