Characterization and simulation of pattern-dependency in ECP topography

• 1、SHANGHAI JIAO TONG UNIVERSITY,SCHOOL OF MICROELECTRONICS
• 2、SHANGHAI HUALI MICROELECTRONICS CORPORATION

Abstract：Electronic Copper Plating (ECP) topography is known affected by layout design and dummy inserting. As consequences of balance among mechanisms associated with different functional ingredients in electroplate liquid, copper can be filled in the trench by the forms of "conformal-fill", "bottom-up" or "supper-fill". Such post ECP topography not only depends on process conditions, but also exhibits strong pattern-related dependency. In this paper, pattern-related effects of ECP topography were characterized with a pre-designed test chip that contains test-keys of line/space arrays of varying line and space widths, and thus varying pattern-density (PD). It was shown that: 1) with fixed PD at 50%, array height (AH) of the test features first decreases with increasing of line-width (LW) when LW is less than 1.0um, and then increases with LW increasing and saturates at LW ~ 3.0um; the step-height (SH) increases with LW, and approaches to trench step height when LW is greater than 3.um. 2) With LW fixed, different trends were observed for narrow lines and wide lines, in both AH and SH vs. varying PD. For narrow lines (LW<0.3um), both AH and SH increase with increasing of PD; while for wide lines (LW>1.0um), both AH and SH decrease with increasing in PD. A semi-empirical model was built to simulate post-ECP topography. It captured all key pattern-dependency in post-ECP AH and SH with acceptable fitting GOF (R2>90%)

Keywords： Microelectronics,Cu ECP, topography, pattern-dependency, line width, pattern density.