高吞吐率LDPC码译码器实现
首发时间:2015-11-17
摘要:采用现场可编程逻辑门阵列(FPGA)实现的低密度奇偶校验(LDPC)码译码器无法充分利用其块随机接入存储器(块RAM或Block RAM)。针对这一问题,设计了一种面向FPGA的可高效利用块RAM的高吞吐率LDPC码译码器。在设计的LDPC译码器中,多个并行译码单元共享块RAM,充分利用了块RAM中闲置的存储单元。进一步,基于FPGA实现了该架构的符合数字地面多媒体广播标准的LDPC码译码器。实现结果表明,实现的译码器能够在不增加电路占用块RAM数量的情况下,达到更高的吞吐量。其中,当工作在100 MHz的时钟频率下时,以译码前的数据量计算,6比特量化译码器的码字吞吐量达到803 Mbps,4比特量化译码器的码字吞吐量达到1.2 Gbps。当误比特率为1e-4时,4比特量化译码器的性能与浮点数译码器的性能相近,性能损失为0.08 dB。
关键词: 低密度奇偶校验码 译码器架构 现场可编程逻辑门阵列 硬件实现
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High throughput LDPC decoder implementation
Abstract:Low-density parity-check (LDPC) decoders implemented with field programmable gate arrays (FPGA) is not able to make full use of block RAMs. To combat this problem, FPGA-based high throughput LDPC decoders which can efficiently utilize the block RAMs are designed. In our decoder, multiple parallel decoding units share the same block RAMs, utilizing the idle storage units. Furthermore, LDPC decoders in digital terrestrial multimedia broadcasting standard are implemented with FPGA. Implementation results show that, the decoders can achieve higher throughput without occupying more block RAMs. When operating at 100 MHz, the 6-bit decoder can achieve the throughput up to 803 Mbps before decoding and the 4-bit decoder can achieve throughput up to 1.2 Gbps. 4-bit quantized decoder achieves the similar performance as the float-point decoders. It only suffers from 0.08 dB degradation when bit error rate is 1e-4.
Keywords: Low-density parity-check code decoder architecture field programmable gate array hardware implementation?????
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No.4660402102505214****
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