High throughput LDPC decoder implementation

• 1、School of Electronic Information Engineering, Tianjin University, Tianjin 300072

Abstract：Low-density parity-check (LDPC) decoders implemented with field programmable gate arrays (FPGA) is not able to make full use of block RAMs. To combat this problem, FPGA-based high throughput LDPC decoders which can efficiently utilize the block RAMs are designed. In our decoder, multiple parallel decoding units share the same block RAMs, utilizing the idle storage units. Furthermore, LDPC decoders in digital terrestrial multimedia broadcasting standard are implemented with FPGA. Implementation results show that, the decoders can achieve higher throughput without occupying more block RAMs. When operating at 100 MHz, the 6-bit decoder can achieve the throughput up to 803 Mbps before decoding and the 4-bit decoder can achieve throughput up to 1.2 Gbps. 4-bit quantized decoder achieves the similar performance as the float-point decoders. It only suffers from 0.08 dB degradation when bit error rate is 1e-4.

Keywords： Low-density parity-check code decoder architecture field programmable gate array hardware implementation?????