垂直沟道纳米线器件的非对称源漏掺杂设计及侧墙结构优化
首发时间:2017-09-01
摘要:本文针对垂直沟道围栅纳米线场效应晶体管,提出了一种涉及源漏延伸区、源漏侧墙k值以及源漏侧墙宽度的器件设计,TCAD(计算机辅助设计软件)仿真结果显示,将源端进行均匀重掺杂的同时,对漏端进行单边的高斯掺杂(掺杂带尾位于沟道一侧),更有利于抑制器件的短沟道,同时提高器件的驱动能力。另外,在漏端采用高k材料,同时适当放宽漏端侧墙宽度,可以将器件的寄生电容控制在较小的同时,进一步降低短沟效应以及提高开态电流。由此可见,垂直沟道的围栅纳米线器件将来应用在低功耗领域具备巨大潜力。
关键词: 微电子学 垂直纳米线 非对称源漏 侧墙k值 寄生电容
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Asymmetric Source/Drain Doping Design and Spacer Optimization For Vertical Channel Nanowire FET
Abstract:In this paper, a source/drain design for vertical channel nanowire FETs involving extension doping profile, spacer dielectric constant and spacer width is proposed and demonstrated by TCAD simulation. The results show that asymmetric graded lightly doped drain (AGLDD) exhibits excellent SCE controllability and driving capability even with relatively large nanowire diameter. By adopting high-k spacer material and optimizing drain spacer width, preferable SCE immunity and higher overdrive current are achieved while parasitic capacitance can be maintained in an acceptable range. This scheme provides a feasible guideline for future low power vertical channel nanowire FETs design.
Keywords: microelectronics vertical nanowire asymmetric source/drain spacer k-value parasitic capacitance
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垂直沟道纳米线器件的非对称源漏掺杂设计及侧墙结构优化
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