55纳米低功耗平台阱注入工艺的光罩缩减方案
首发时间:2018-05-21
摘要:集成电路产业的蓬勃发展带来各家公司之间的良性竞争,芯片生产成本的降低成为各家公司争先研究的方向。本文提出了一种降低55纳米低功耗平台成本的可行方法。在现有工艺流程的基础上,对逻辑区和存储区的高阈值晶体管的阱注入光罩进行合并,从而实现量产品工艺的优化和精简。通过大量数据收集和理论计算,给出了一种既不影响逻辑区高阈值晶体管工作,又能保证储存器件正常工作的方案,并通过流片验证,证明了该模型的可靠性和可行性。可将该方案并行推广至55纳米低功耗平台有高阈值开启器件和静态储存器件的所有产品。
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55LP Mask Reduction for Well Loop
Abstract:This paper proposes a feasible way to decrease the cost of 55 nanometer low-power platform. On the basis of the existing technological process, the logic of the threshold of a 10-degree patch area and storage transistor well into the mask to merge, so as to realize the optimization of quantity of product process and streamlined. Through a lot of data collection and calculation, this paper gives a kind of both neither affect work, high threshold logic transistor can guarantee the normal work of the storage devices, and through the flow verification, proved the reliability and feasibility of the model. The scheme can be parallel to 55 nanometer low-power platform has high threshold open device and static storage device of all the products.
Keywords: well IMP mask reduction WAT matching
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