Design of a MIPI protocol high-speed interface D-PHY physical layer circuit

• 1、School of Microelectronics, Dalian University of Technology, Dalian 116024

Abstract：MIPI is a flexible source-synchronous serial interface standard used to connect displays and camera modules on a host or mobile device. It has the advantages of low power consumption, high-rate transmission, and strong anti-electromagnetic interference capabilities. The physical layer of MIPI directly affects the transmission rate and quality of the signal. In this article, the SMIC 0.18μm CMOS technology is used to design a faster and better performance MIPI D-PHY physical layer circuit for high-speed interfaces. It includes clock channel circuit with duty-cycle correction, high-speed transmitter circuit, high-speed receiver circuit, low-power transmitter circuit, low-power receiver circuit and low-power conflict detector circuit. The simulation results of each module meet the requirements of the MIPI protocol specification. In high-speed mode, the accuracy of clock duty-cycle correction is ±0.5%, the single-channel signal transmission rate reaches 2Gbps, and in low-power mode, the signal transmission rate is not more than 10Mbps, the power consumption is 2.8mW, and the jitter is only 8ps, far less than the standard 32ps.

Keywords： MIPI D-PHY Physical layer Duty-cycle correction High speed Low jitter