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期刊论文
An Efficient Packet Fair Queueing(PFQ) Architecture for Latency Rate Server*
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Queuing/scheduling algorithm is one of the most important mechanisms to provide guaranteed Quality of Service(QoS) in high speed packet-switched networks. By computing the system virtual time and per packet/connection virtual start/finish time, a number of Packet Fair Queueing(PFQ) algorithms are designed to simulate GPS (Generalized Processor Sharing)[1]. The difference in computation complexity is due to the variable ways to compute system time. Many algorithms, including WFQ/WF2Q, SCFQ, SPFQ, WF2Q+, VC, etc., have been proposed to use different system Virtual Time(also known as system potential) function. This paper proves that all the Latency-Rate (LR) servers only need to calculate their system virtual times once per packet service time, no matter how many packet arrivals occur in this interval. Thus, it is a general scheme that benefits all the well-known LR PFQ algorithms.
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