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期刊论文

An Efficient Packet Fair Queueing(PFQ) Architecture for Latency Rate Server*

程时端Haitao Wu Shiduan Cheng Jian Ma

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摘要/描述

Queuing/scheduling algorithm is one of the most important mechanisms to provide guaranteed Quality of Service(QoS) in high speed packet-switched networks. By computing the system virtual time and per packet/connection virtual start/finish time, a number of Packet Fair Queueing(PFQ) algorithms are designed to simulate GPS (Generalized Processor Sharing)[1]. The difference in computation complexity is due to the variable ways to compute system time. Many algorithms, including WFQ/WF2Q, SCFQ, SPFQ, WF2Q+, VC, etc., have been proposed to use different system Virtual Time(also known as system potential) function. This paper proves that all the Latency-Rate (LR) servers only need to calculate their system virtual times once per packet service time, no matter how many packet arrivals occur in this interval. Thus, it is a general scheme that benefits all the well-known LR PFQ algorithms.

【免责声明】以下全部内容由[程时端]上传于[2005年01月26日 21时27分18秒],版权归原创者所有。本文仅代表作者本人观点,与本网站无关。本网站对文中陈述、观点判断保持中立,不对所包含内容的准确性、可靠性或完整性提供任何明示或暗示的保证。请读者仅作参考,并请自行承担全部责任。

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