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期刊论文

An implementation of sustained reabtime radar data recording system on FPGA+

贾惠波He Ning * Wang Hun Xiong Jianping Jiang Changlong Jia Huibo

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摘要/描述

This paper presents a new architecture for high-speed sustained data recording system, in which real-time and high throughput arc two key points. The FPGA implementation of the system controller is given as well. After the I/O bottleneck of conventional storage system structure is analyzed in this paper, a new recording and storage system framework is put forward by aiming to shorten the data transfer path and consequently to reduce the system resource utilization and data transfer latency, contrarily resulting in the improvement of the sustained data recording speed. To satisfy the real-time requirement, a local bus central logic controller module is designed to take the role of former host-side software and to reduce the utilization of host resource and latency caused by the intervention of the host. A speed-matching logic module between the disk in burst transfer mode and the sustained source acquisition data stream is also designed and implemented on a single FPGA chip. The proposed architecture and implementation approaches can be adapted in many applications where real-time and high I/O throughput are required.

【免责声明】以下全部内容由[贾惠波]上传于[2005年02月25日 19时42分36秒],版权归原创者所有。本文仅代表作者本人观点,与本网站无关。本网站对文中陈述、观点判断保持中立,不对所包含内容的准确性、可靠性或完整性提供任何明示或暗示的保证。请读者仅作参考,并请自行承担全部责任。

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