An implementation of sustained reabtime radar data recording system on FPGA+
This paper presents a new architecture for high-speed sustained data recording system, in which real-time and high throughput arc two key points. The FPGA implementation of the system controller is given as well. After the I/O bottleneck of conventional storage system structure is analyzed in this paper, a new recording and storage system framework is put forward by aiming to shorten the data transfer path and consequently to reduce the system resource utilization and data transfer latency, contrarily resulting in the improvement of the sustained data recording speed. To satisfy the real-time requirement, a local bus central logic controller module is designed to take the role of former host-side software and to reduce the utilization of host resource and latency caused by the intervention of the host. A speed-matching logic module between the disk in burst transfer mode and the sustained source acquisition data stream is also designed and implemented on a single FPGA chip. The proposed architecture and implementation approaches can be adapted in many applications where real-time and high I/O throughput are required.
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