This paper presents FSimGEO, an efficient test generation method for path delay fault test using Fault Simulation and Genetic Optimization. A parallel-vector fault simulator is introduced first, which can simulate several test vector pairs at the same time through introducing a four-valued logic and the Path Status Graph (PSG) of the circuit structure. After this, a special genetic optimization algorithm is used to direct the process of searching and to optimize test sets generated. We have given the fitness function and genetic operators that affect the optimizing efficiency of Genetic Algorithm (GA) in detail. Experiment results have showed that the number of path tested by FSimGEO is about 3.5 times by latter one.