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王志功
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期刊论文
A 0.35um CMOS 6.1GHz 1:4 Static Frequency Divider
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A 1:4 static frequency divider has been designed and realized in a 0.35-micron standard CMOS technology. The chip consists of two identical 1:2 divider cells, which are based on SCL (Source Coupled Logic) flip-flops. By revising the traditional topology of SCL flip-flop, we get a divider with better perforrrmances. Mesurement results show that the whole chip achieves the frequency division at more than 6GHz. Each 1:2 divider consumes llmW from a 3.3V supply. The divider can be used in RF and Optic-fiber Transceivers and othex high-speed systems.
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