A cascaded 1:10 demuldplexer with comma detection and word alignment has been developed and fabricated using a 0.25gin CMO$ technology. It operates at half the clock frequency of the input data and uses a word alignment clock divider to ensure the parallel data output at the word boundary. Tested on wafer, the chip can operate from IGb/s to 3,125Gb/s to meet various specifications, The measured peak-peak voltage is above 700mV based on 50 load and the phase jitter is l lps rms at the 3.125-Gb/s standard input bit rate. The power consumption is 234mW with a 3.3V supply and the chip area 1.3mm2.