As ultra large scale integration devices scale to smaller feature sizes and larger die dimensions, the resistance-capacitance (RC) delay of the metal interconnections will increasingly limit the performance of high speed logic chips. In order to reduce the RC delay, the introduction of low dielectric constant (k) materials (k<3) for the interlayer dielectric and/or low-resistivity conductors, such as copper, is required. [1] In order to reduce the interconnection capacitance, many low k materials have been developed using different methods, such as CVD, spin coating, liquid-phase deposition, porous film formation techniques, and air bridge techniques. [2] Of particular interest are CVD techniques, which have the advantage of being able to completely fill narrow features with a high aspect ratio better than other deposition techniques, and are also generally considered compatible with damascene process flows. Furthermore, a layered structure that promotes adhesion can be easily fabricated by changing the source compounds, so the deposition of low k thin films by CVD appears promising. As Dorfman suggested, [3] in atomicscale composites the highest physical limits of mechanical and electronic "sensor" properties can be combined, leading to the creation of "smart" construction materials. For instance, diamond-like atomic-scale composites (a-C:H/a-Si:O) and metal-containing, diamond-like nanocompos-