Vertically aligned Si nanoconstrictions have potential for applications of electronic, photonic and phononic nanodevices. Herein, we report a featured method by utilizing the non-uniaxial tangential tension stress (σT) at the Si surface of a vertical hyperbolic Si/SiO2 core–shell nanostructure during thermal oxidation to achieve well defined Si nanoconstrictions. A thermal oxidation model was proposed to describe the correlations between σT and the structural parameters of the hyperbolic nanostructure, i.e. oxide thickness (tox), sidewall curvature radius (R0) and neck diameter (2rA0). Numerical simulations indicated that the Si surface at the position with the narrowest diameter (neck position) has the highest σT (~GPa) and presents a gradient distribution at both ends. By means of stress regulation, an array of well defined Si nanoconstrictions about 10 nm in diameter and about 34 nm in length was obtained. The experimental findings demonstrated that the high σT would induce a nanofracture and thus a local oxidation to form a nanoconstriction, self-aligned at the neck position. The finding notably extends the capability of stress-assisted 'nanofabrication' of Si via thermal oxidation.

The improving of tip-to-tip electron emission uniformity in an array is one of the essential issues for the vacuum microelectronic/nanoelectronic applications. Here, we report the achieving of quasi-saturated ultrahigh arsenic concentration (-.6.7 × 1021/cm 3 ) at the Si nanotip apex, in the mechanisms of dopant segregation during the thermal oxidation and the limitation of arsenic solubility in Si. The tips with quasi-saturated high-level arsenic concentration possess a well tip-to-tip uniformity in surface work function. The measured work function for the tips in an array with saturated dopant concentration is in a narrow range of 4.347-4.371 eV (-.2.1% fluctuation). This merit not only resulted in high emission current density (-.418.36 mA/cm 2 ) from the devices at a relatively lower gate voltage but also brought well spatially uniform electron emission in an array. The work inspired vital insight into the interpretation for mechanisms in dopant density control and the improving of emission uniformity of the Si-tip array. It could be used as an essential approach to acquire high-performance Si-based vacuum electronic devices.

Thermo-enhancement is an effective way to achieve high performance field electron emitters, and enables the individually tuning on the emission current by temperature and the electron energy by voltage. The field emission current from metal or n-doped semiconductor emitter at a relatively lower temperature (i.e., < 1000 K) is less temperature sensitive due to the weak dependence of free electron density on temperature, while that from p-doped semiconductor emitter is restricted by its limited free electron density. Here, we developed full array of uniform individual p-Si/ZnO nanoemitters and demonstrated the strong thermo-enhanced field emission. The mechanism of forming uniform nanoemitters with well Si/ZnO mechanical joint in the nanotemplates was elucidated. No current saturation was observed in the thermo-enhanced field emission measurements. The emission current density showed about ten-time enhancement (from 1.31 to 12.11 mA/cm2 at 60.6 MV/m) by increasing the temperature from 323 to 623 K. The distinctive performance did not agree with the interband excitation mechanism but well-fit to the band-to-band tunneling model. The strong thermo-enhancement was proposed to be benefit from the increase of band-to-band tunneling probability at the surface portion of the p-Si/ZnO nanojunction. This work provides promising cathode for portable X-ray tubes/panel, ionization vacuum gauges and low energy electron beam lithography, in where electron-dose control at a fixed energy is needed.

Well-shaped micro/nano-structured suspended graphene is a versatile building block for micro/nano-electromechanical (MEMS/NEMS) devices. Directly 'sculpting' the suspended graphene membrane using an accelerated energetic electron/ion beam to form micro/nano-structured graphene possesses the merits of high resolution and well-processed flexibility. However, both the residual and process-induced stress in the membrane still challenge the obtaining of non-distorted freestanding graphene patterns. We report a featured double-sided masking and stress-release etching method to fabricate well-defined suspended graphene micro-ribbon. We demonstrated that the one-step low-energy (10 keV) electron beam induced the deposition of amorphous carbon (a-C) on both sides of the suspended graphene. The a-C layers were precisely self-aligned, not only allowing its use as reliable masks for the following plasma etch of suspended graphene, but showing potential for future applications of effectively 'writing' circuits/devices directly on both sides of a suspended 2D atomic-layered platform. A stress-release plasma etching process and its 'self-crumpling' mechanism were demonstrated. High-aspect-ratio micro-structured graphene (bridge and cantilever) with a good shape was obtained. This provides a promising and universal processing method for making suspended structures of 2D materials with in-plane flatness for potential MEMS/NEMS applications.

Graphene with atomic sharp edges have been widely studied to demonstrate that it is an ideal material for field electron emission (FEE). However, FEE performance of graphene film with wrinkled or crumpled tip-structures is still unknown. Here, we introduce a facile method to fabricate wrinkled graphene (WG) at the liquid-air interface. The graphene synthesized by chemical vapor deposition self-shrinks into WG on the surface of ethanol/deionized water solution. The morphology, height and distribution of wrinkles in WG can be conveniently controlled by modulating the vertical temperature gradient of the solution. According to the theoretical analysis, the self-assembly of WG is due to the energy transfer from the decreasing Gibbs free energy and the work done by Rayleigh-Bénard convection to the bending strain energy of WG. The substrate-independent formation of WG enables its direct transfer onto arbitrary hydrophilic surfaces to greatly enhance the hydrophobicity. Furthermore, the as-prepared WG shows more excellent FEE performance in comparison of the pristine graphene. The WG with higher wrinkles show a lower turn-on field, higher field enhancement factor and stable emission current. We believe that the method is potential to be universally applied in the manufacture of microstructures on other 2D materials for facilitating their practical applications.

Optical complex materials offer unprecedented opportunity to engineer fundamental band dispersion, which enables novel optoelectronic functionality and devices. Exploration of the photonic Dirac cone at the center of momentum space has inspired an exceptional characteristic of zero index, which is similar to zero effective mass in Fermionic Dirac systems. Such all-dielectric zero-index photonic crystals provide an in-plane mechanism such that the energy of the propagating waves can be well confined along the chip direction. A straightforward example is to achieve the anomalous focusing effect without longitudinal spherical aberration when the size of the zero-index lens is large enough. Here, we designed and fabricated a prototype of a zero-refractive-index lens by using a large-area silicon nanopillar array with a plane-concave profile. The near-zero refractive index was quantitatively measured near 1550 nm through the anomalous focusing effect, predictable by effective medium theory. The zero-index lens was also demonstrated to have ultralow longitudinal spherical aberration. Such an integrated-circuit-compatible device provides a new route to integrate all-silicon zero-index materials into optical communication, sensing, and modulation and to study fundamental physics in the emergent fields of topological photonics and valley photonics.

We report the featured gated field electron emission devices of Si nano-tips with individually integrated Si nano-channels and the interpretation of the related physics. A rational procedure was developed to fabricate the uniform integrated devices. The electrical and thermal conduction tests demonstrated that the Si nano-channel can limit both the current and heat flows. The integrated devices showed the specialties of self-enhancement and self-regulation. The heat resistance results in the heat accumulation at the tip-apex, inducing the thermally enhanced field electron emission. The self-regulated effect of the electrical resistance is benefit for impeding the current overloading and prevents the emitters from a catastrophic breakdown. The nano-channel-integrated Si nano-tip array exhibited emission current density up to 24.9 mA/cm2 at a gate voltage of 94 V, much higher than that of the Si nano-tip array without an integrated nano-channel. This work was supported in part by the projects from the National Key Basic Research Program of China (Grant No. 2013CB933601), the National Natural Science Foundation of China (Grant No. 51272293), the Science and Technology and Information Department of Guangzhou City (Grant No. 201607020012), the SYSU-CMU Shunde International Joint Research Institute (20150201), and The Fundamental Research Funds for the Central Universities of China (15lgjc25).

The development of high performance nano-electron-emitter arrays with well reliability still proves challenging. Here, we report a featured integrated nano-electron-emitter. The vertically aligned nano-emitter consists of two segments. The top segment is an intrinsically lightly n-type doped ZnO nano-tip, while the bottom segment is a heavily p-type doped Si nano-pillar (denoted as p-Si/ZnO nano-emitter). The anode voltage not only extracted the electron emission from the emitter apex but also induced the inter-band electron tunneling at the surface of the p-Si/ZnO nano-junction. The designed p-Si/ZnO emitter is equivalent to a ZnO nano-tip individually ballasted by a p-Si/ZnO diode and a parasitic tunneling field effect transistor (TFET) at the surface of the p-Si/ZnO junction. The parasitic TFET provides a channel for the supply of emitting electron, while the p-Si/ZnO diode is benefit for impeding the current overloading and prevent the emitters from a catastrophic breakdown. Well repeatable and stable field emission current were obtained from the p-Si/ZnO nano-emitters. High performance nano-emitters was developed using diamond-like-carbon coated p-Si/ZnO tip array (500 × 500), i.e., 178 μA (4.48 mA/cm2) at 75.7 MV/m.

Nano-scale vacuum channel transistors possess merits of higher cutoff frequency and greater gain power as compared with the conventional solid-state transistors. The improvement in cathode reliability is one of the major challenges to obtain high performance vacuum channel transistors. We report the experimental findings and the physical insight into the field induced crystalline-to-amorphous phase transformation on the surface of the Si nano-cathode. The crystalline Si tip apex deformed to amorphous structure at a low macroscopic field (0.6~1.65 V/nm) with an ultra-low emission current (1~10 pA). First-principle calculation suggests that the strong electrostatic force exerting on the electrons in the surface lattices would take the account for the field-induced atomic migration that result in an amorphization. The arsenic-dopant in the Si surface lattice would increase the inner stress as well as the electron density, leading to a lower amorphization field. Highly reliable Si nano-cathodes were obtained by employing diamond like carbon coating to enhance the electron emission and thus decrease the surface charge accumulation. The findings are crucial for developing highly reliable Si-based nano-scale vacuum channel transistors and have the significance for future Si nano-electronic devices with narrow separation.

A featured “vapor transportation” assembly technique was developed to attain layer-by-layer stacking continuous graphene oxide (GO) films on both flat and concavo-concave surfaces. Few-layer (layer number < 10) GO sheets were “evaporated” (carried by water vapor) from the water-dispersed GO suspension and smoothly/uniformly tiled on the substrate surface. We have found evidence of the influence of the deposition time and substrate–liquid separation on the film thickness. A model was proposed for interpreting the assembly process. It was found that a current conditioning would induce a reduction of the GO surface and form an Ohmic contact between the GO–metal interfaces. Accordingly, an actively modulated GO cold cathode was fabricated by locally depositing continuous GO sheets on the drain electrode of a metal-oxide-semiconductor field effect transistor (MOSFET). The field emission current of the GO cathode can be precisely controlled by the MOSFET gate voltage (VGS). A current modulation range from 1 × 10−10 A to 6.9 × 10−6 A (4 orders of magnitude) was achieved by tuning the VGS from 0.812 V to 1.728 V. Due to the self-acting positive feedback of the MOSFET, the emission current fluctuation was dramatically reduced from 57.4% (non-control) to 3.4% (controlled). Furthermore, the integrated GO cathode was employed for a lab-prototype display pixel application demonstrating the active modulation of the phosphor luminance, i.e. from 0.01 cd m−2 to 34.18 cd m−2.