

廖蕾
博士 教授 博士生导师
湖南大学 物理与微电子科学学院
微电子学与固体电子学,半导体电子器件和光电子器件
个性化签名
- 姓名:廖蕾
- 目前身份:在职研究人员
- 担任导师情况:博士生导师
- 学位:博士
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学术头衔:
博士生导师, 教育部“新世纪优秀人才支持计划”入选者
- 职称:高级-教授
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学科领域:
半导体技术
- 研究兴趣:微电子学与固体电子学,半导体电子器件和光电子器件
廖蕾,男,1981年10月出生,博士,湖南大学物理与微电子科学学院教授,博士生导师。主要开展高性能纳电子器件的研究。
教育背景
2000年-2004年 武汉大学物理学院 本科;
2004年-2009年 武汉大学物理学院硕博连读,导师:李金钗 教授;
2005年-2007年 中国科学院物理所 联合培养,导师:王恩哥/白雪冬 教授。
工作履历
2007年-2009年南洋理工大学 千禧研究员 导师:申泽襄/于霆 教授
2009年-2011年加州大学洛杉矶分校 博士后,导师:段镶锋 教授
2011年-2016年武汉大学物理学院 教授,微电子系 系主任
2017年-2020年 湖南大学物理与微电子科学学院 教授,微纳光电器件与应用教育部重点实验室 主任,学院副院长
2020年-现在 湖南大学物理与微电子科学学院 教授,微纳光电器件与应用教育部重点实验室 主任,研究生院副院长/培养办主任
学术兼职
Fellow of the Institution of Engineering and Technology (IET)
SID(国际信息显示协会)北京分会专业技术委员会委员
Senior Member of IEEE
Journal of Physics D: Applied Physics 编委会成员
Chinese Physics Letters “半导体电子器件”编辑和编委会成员
科研项目
主持国家重点研发计划课题,国家自然科学基金委JQ项目,大科学装置联合基金培育项目,面上项目和湖南省自然科学基金创新群体项目等。
作为科研骨干参加科技部重点基础研究发展计划(973),重大科学研究计划纳米专项,重点研发计划和国家重大专项。
学术成果
发表论文200多篇,主要在Nature、Nature Electron.、Nature Commun.、Adv. Mater.、Nano Lett.和IEEE EDL/TED等期刊上,总他引次数超过10000次,H因子65。
奖励与荣誉
英国工程技术学会会士(Fellow of IET)
全球高被引学者 (2018/2020)
国家自然科学基金委JQ项目
湖南省自然科学基金创新群体项目
湖南省湖湘青年英才
中国侨联贡献奖
湖北省自然科学一等奖(排名第二)
全国百篇优秀博士论文提名奖
教育部新世纪优秀人才支持计划
新加坡千禧奖
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主页访问
5
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关注数
0
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成果阅读
61
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成果数
20
【期刊论文】High-κ oxide nanoribbons as gate dielectrics for high mobility top-gated graphene transistors
PNAS,2010,107(15):6711-6715
2010年04月13日
Deposition of high-κ dielectrics onto graphene is of significant challenge due to the difficulties of nucleating high quality oxide on pristine graphene without introducing defects into the monolayer of carbon lattice. Previous efforts to deposit high-κ dielectrics on graphene often resulted in significant degradation in carrier mobility. Here we report an entirely new strategy to integrate high quality high-κ dielectrics with graphene by first synthesizing freestanding high-κ oxide nanoribbons at high temperature and then transferring them onto graphene at room temperature. We show that single crystalline Al2O3 nanoribbons can be synthesized with excellent dielectric properties. Using such nanoribbons as the gate dielectrics, we have demonstrated top-gated graphene transistors with the highest carrier mobility (up to 23,600 cm2/V·s) reported to date, and a more than 10-fold increase in transconductance compared to the back-gated devices. This method opens a new avenue to integrate high-κ dielectrics on graphene with the preservation of the pristine nature of graphene and high carrier mobility, representing an important step forward to high-performance graphene electronics.
graphene dielectric integrationcarrier mobilitydielectric nanoribbonnanoelectronics
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【期刊论文】High-speed graphene transistors with a self-aligned nanowire gate
Nature ,2010,467():305–308
2010年09月01日
Graphene has attracted considerable interest as a potential new electronic material1,2,3,4,5,6,7,8,9,10,11. With its high carrier mobility, graphene is of particular interest for ultrahigh-speed radio-frequency electronics12,13,14,15,16,17,18. However, conventional device fabrication processes cannot readily be applied to produce high-speed graphene transistors because they often introduce significant defects into the monolayer of carbon lattices and severely degrade the device performance19,20,21. Here we report an approach to the fabrication of high-speed graphene transistors with a self-aligned nanowire gate to prevent such degradation. A Co2Si–Al2O3 core–shell nanowire is used as the gate, with the source and drain electrodes defined through a self-alignment process and the channel length defined by the nanowire diameter. The physical assembly of the nanowire gate preserves the high carrier mobility in graphene, and the self-alignment process ensures that the edges of the source, drain and gate electrodes are automatically and precisely positioned so that no overlapping or significant gaps exist between these electrodes, thus minimizing access resistance. It therefore allows for transistor performance not previously possible. Graphene transistors with a channel length as low as 140 nm have been fabricated with the highest scaled on-current (3.32 mA μm−1) and transconductance (1.27 mS μm−1) reported so far. Significantly, on-chip microwave measurements demonstrate that the self-aligned devices have a high intrinsic cut-off (transit) frequency of fT = 100–300 GHz, with the extrinsic fT (in the range of a few gigahertz) largely limited by parasitic pad capacitance. The reported intrinsic fT of the graphene transistors is comparable to that of the very best high-electron-mobility transistors with similar gate lengths10.
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【期刊论文】Scalable Fabrication of Self-Aligned Graphene Transistors and Circuits on Glass
Nano Lett.,2011,12(6):2653–2657
2011年06月07日
Graphene transistors are of considerable interest for radio frequency (rf) applications. High-frequency graphene transistors with the intrinsic cutoff frequency up to 300 GHz have been demonstrated. However, the graphene transistors reported to date only exhibit a limited extrinsic cutoff frequency up to about 10 GHz, and functional graphene circuits demonstrated so far can merely operate in the tens of megahertz regime, far from the potential the graphene transistors could offer. Here we report a scalable approach to fabricate self-aligned graphene transistors with the extrinsic cutoff frequency exceeding 50 GHz and graphene circuits that can operate in the 1–10 GHz regime. The devices are fabricated on a glass substrate through a self-aligned process by using chemical vapor deposition (CVD) grown graphene and a dielectrophoretic assembled nanowire gate array. The self-aligned process allows the achievement of unprecedented performance in CVD graphene transistors with a highest transconductance of 0.36 mS/μm. The use of an insulating substrate minimizes the parasitic capacitance and has therefore enabled graphene transistors with a record-high extrinsic cutoff frequency (> 50 GHz) achieved to date. The excellent extrinsic cutoff frequency readily allows configuring the graphene transistors into frequency doubling or mixing circuits functioning in the 1–10 GHz regime, a significant advancement over previous reports (∼20 MHz). The studies open a pathway to scalable fabrication of high-speed graphene transistors and functional circuits and represent a significant step forward to graphene based radio frequency devices.
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Nano Lett.,2012,12(7):3596–3601
2012年06月13日
Here we report unique performance transistors based on sol–gel processed indium zinc oxide/single-walled carbon nanotube (SWNT) composite thin films. In the composite, SWNTs provide fast tracks for carrier transport to significantly improve the apparent field effect mobility. Specifically, the composite thin film transistors with SWNT weight concentrations in the range of 0–2 wt % have been investigated with the field effect mobility reaching as high as 140 cm2/V·s at 1 wt % SWNTs while maintaining a high on/off ratio ∼107. Furthermore, the introduction SWNTs into the composite thin film render excellent mechanical flexibility for flexible electronics. The dynamic loading test presents evidently superior mechanical stability with only 17% variation at a bending radius as small as 700 μm, and the repeated bending test shows only 8% normalized resistance variation after 300 cycles of folding and unfolding, demonstrating enormous improvement over the basic amorphous indium zinc oxide thin film. The results provide an important advance toward high-performance flexible electronics applications.
Indium zinc oxide carbon nanotubes transistor high mobility flexible
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Nano Lett.,2013,13(7):3287–3292
2013年06月24日
“One key to one lock” hybrid sensor configuration is rationally designed and demonstrated as a direct effective route for the target-gas-specific, highly sensitive, and promptly responsive chemical gas sensing for room temperature operation in a complex ambient background. The design concept is based on three criteria: (i) quasi-one-dimensional metal oxide nanostructures as the sensing platform which exhibits good electron mobility and chemical and thermal stability; (ii) deep enhancement-mode field-effect transistors (E-mode FETs) with appropriate threshold voltages to suppress the nonspecific sensitivity to all gases (decouple the selectivity and sensitivity away from nanowires); (iii) metal nanoparticle decoration onto the nanostructure surface to introduce the gas specific selectivity and sensitivity to the sensing platform. In this work, using Mg-doped In2O3 nanowire E-mode FET sensor arrays decorated with various discrete metal nanoparticles (i.e., Au, Ag, and Pt) as illustrative prototypes here further confirms the feasibility of this design. Particularly, the Au decorated sensor arrays exhibit more than 3 orders of magnitude response to the exposure of 100 ppm CO among a mixture of gases at room temperature. The corresponding response time and detection limit are as low as ∼4 s and ∼500 ppb, respectively. All of these could have important implications for this “one key to one lock” hybrid sensor configuration which potentially open up a rational avenue to the design of advanced-generation chemical sensors with unprecedented selectivity and sensitivity.
In2O3 nanowires transistors enhancement-mode gas sensors selectivity
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【期刊论文】Interface Engineering for High‐Performance Top‐Gated MoS2 Field‐Effect Transistors
Adv. Mater. ,2014,26(36):6255-6261
2014年07月28日
Experimental evidence of the optimized interface engineering effects in MoS2 transistors is demonstrated. The MoS2/Y2O3/HfO2 stack offers excellent interface control. Results show that HfO2 layer can be scaled down to 9 nm, yet achieving a near‐ideal sub‐threshold slope (65 mv/dec) and the highest saturation current (526 μA/μm) of any MoS2 transistor reported to date.
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Adv. Mater.,2014,26(43):7399-7404
2014年09月18日
A high mobility of 109.0 cm2 V−1 s−1 is obtained by thin‐film transistors (TFTs) comprising a composite made by aligning SnO2 nanowires (NWs) in amorphous InGaZnO (a‐IGZO) thin films. This composite TFT reaches an on‐current density of 61.4 μA μm−1 with a 10 μm channel length. Its performance surpasses that of single‐crystalline InGaZnO and is comparable with that of polycrystalline silicon.
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Small,2014,11(2):208-213
2014年08月13日
Charge trapping layers are formed from different metallic nanocrystals in MoS2‐based nanocrystal floating gate memory cells in a process compatible with existing fabrication technologies. The memory cells with Au nanocrystals exhibit impressive performance with a large memory window of 10 V, a high program/erase ratio of approximately 105 and a long retention time of 10 years.
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Adv. Mater.,2016,28(10):2062-2069
2016年01月13日
A unique design of a hexagonal boron nitride (h‐BN)/HfO2 dielectric heterostructure stack is demonstrated, with few‐layer h‐BN to alleviate the surface optical phonon scattering, followed by high‐κ HfO2 deposition to suppress Coulombic impurity scattering so that high‐performance top‐gated two‐dimensional semiconductor transistors are achieved. Furthermore, this dielectric stack can also be extended to GaN‐based transistors to enhance their performance.
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Adv. Mater.,2016,28(37):8302-8308
2016年07月08日
High‐performance MoS2 transistors are developed using atomic hexagonal boron nitride as a tunneling layer to reduce the Schottky barrier and achieve low contact resistance between metal and MoS2. Benefiting from the ultrathin tunneling layer within 0.6 nm, the Schottky barrier is significantly reduced from 158 to 31 meV with small tunneling resistance.
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