本文介绍了一种集成电路芯片瞬时功率测量-采集-分析系统。这是一种基于普通设备搭建的软硬件结合的测试系统。文中详细介绍了系统的测量方案，以及系统组成和各部分的功能与实现，并给出了需要注意的细节。

集成电路的工作功率与其处理数据间的相关性是“功耗分析攻击”[1]的物理基础。本文分析了CMOS电路的状态和输入数据影响电路功耗的各种机制——其中考虑了静态电流、信号变化速率等因素，给出了一个动态CMOS逻辑门瞬态电流与数据间的相关关系模型。并由它推算基本逻辑门工作电流的信息量，与仿真结果进行了对比说明。本文主要结论包括：N型动态电路具有更高的安全性；次开启电流、短路电流同样可以泄漏数据信息；电源电流还可能泄漏上次运算和前级电路所处理数据的部分信息等。

差分功耗分析是一种针对密码芯片的攻击手段，它通过分析功耗信息提取芯片密钥。功耗平衡的实现方法可以提供抗功耗攻击的加密硬件。本文介绍了一种由功耗平衡模块组成的延时不敏感（DI）超前进位加法器，这些功耗平衡模块的工作功耗与输入数据无关。本设计的特点是在晶体管级进行功耗平衡。文中给出了功耗平衡模块和普通模块的功耗差分，对比显示电路改进后的模块更安全。

This paper describes a new scalable architecture of Montgomery modular multiplier (MMM) using our improved FIOS algorithm. This algorithm and architecture can manipulate operands of any precision (bit length) in dual field (prime field and binary field) and has the advantage of using relatively smaller latency (clock cycles) to complete one modular multiplication. Our architecture is reusable and has high performance with respect to latency, timing, area, etc.

Application specific on-chip network is a promising direction for Networks on Chips (NoCs) to solve the interconnection challenges that Systems on Chips (SoCs) will encounter in the billion-transistor age. This paper presents a novel design methodology named On-Chip Network Evolution, which helps developing an on-chip network rapidly according to a specific application. To explore the network design space more efficiently, a new description language-NetC is introduced, which is a group of syntaxes that can be translated into SystemC programs.

This paper presents a novel architecture of register files that combines the local register files and the global register file for clustered VLIW (Very Long Instruction Word) processors. The communication between function units through global register file will be more efficient. The concept of associate register is introduced for this architecture. This makes it possible to write a result to two destination registers in one operation, which can efficiently speed up the software pipelining.

In this paper, a new systematic method to synthesize the low-complexity and low-power realization of high-order FIR filters in VLSI was proposed. First, FIR filter was reprensented in graph, and the coefficients were reordered to generate a optimal realization structure using minimum spanning tree algorithm. Then the common subexpressions in the multiple constant multiplier array were extracted and reused to get further reduction in computational complexity. Finally, we gave some results of proposed method to demonstrate its effectiveness and high efficiency in synthesis of FIR filter in VLSI.We have achieved 36% reduction in implementation complexity without performance degradation.

For speech processing applications such as speech coding or speech recognition, Gabor transform has been a more and more important tool to rid the speech signal of redundancy. A new ASIC design of Gabor transform for speech processing is presented in this paper. To implement the high-speed operation of Gabor transform, some special architectures are designed. The control part of the system can configure the arithmetic units to adapt to variant operation requirement such as input of different points and processing Gabor transform or inverse-Gabor transform. The design is implemented by using ASIC technology.

In this paper, a novel algorithm called logic depth oriented (LDO) common subexpression elimination (CSE) is proposed. In order to avoid the increase of logic depth in circuit structure that may be caused by the application of some other CSE techniques, the process of common subexpressions eliminating of this algorithm is logic depth oriented and the realization of logic operators reuse will not lead to the increase of logic depth. A complete description of the LDO algorithm and the comparisons with several popular CSE algorithms are presented in this paper. Results of comparisons show that using this algorithm can realize the logic operators reuse efficiently, while the logic depth in circuit structure will maintain optimal. Application of this method in the multiplierless VLSI implementation of high-speed FIR filters or some other multiple constant multiplication (MCM) problems will contribute to the high performances in several aspects such as area, speed and power dissipation.

In this article, the estimation of Harmonic to Noise Ratio (HNR) in transmitted sound signals with wavelet transform was proposed. When subjects phonate sustained vowels in breathy, falsetto, leakage and pressed mode in normal loudness, the HNR in human voice and transmitted sound signals was estimated and compared. The results indicated that the NHR in transmitted sound signals could accurately image vocal folds vibration modes and characteristics. It would be one of useful measurements for clinical laryngeal disease diagnosis.