Considerably suppressed gate-induced drain leakage (GIDL) shifts of N2O-based n-MOS-FET's after hot-carrier stress with different gate voltages are observed. The mechanisms involved are studied by dividing gate-oxide traps into sub-interface and bulk-oxide traps, and by means of computer simulations on electric-field distribution and carrier filling of these traps. It is demonstrated that sub-interface and bulk-oxide hole detrapping during stressing are mainly responsible for the respective GIDL shifts under two diff erent stress conditions of VG=0.5VD and VG=VD, with the effect of the former larger than the latter. In view of this, it is proposed that MOSFET's with N2O-nitrided or es-pecially N2O-annealed NH3-nitrided gate oxide have not only fewer pre-existing sub-interface and bulk-oxide hole traps, but also greatly suppressed generation of hole and neutral electron traps due to the formation of a nitrogen-rich layer near the SiO2/Si interface through N2O treatment.

Oxynitrides prepared by double nitridation in nitric oxide (NO) and nitrous oxide (N2O) are compared to the one with a single NO nitridation. Based on various hot-carrier stresses, harder oxide/Si interface, less charge trapping and generation of electron/hole traps in oxide, and larger chargeto-breakdown are observed for the doubly-nitrided gate dielectrics than the singly-nitrided one. By analyzing the nitrogen profiles in these oxynitrides, it is revealed that the involved mechanisms lie in the smaller distance of peak nitrogen concentration from the oxide/Si interface and the higher nitrogen content near the oxide=Si interface in the doublynitrided oxynitrides.

The energy levels of interface states generated in n-MOSFETs during hot-carrier stressings under maximum substrate-current condition (VG～VD/2) are studied by measuring their GIDL current, which is believed to result from trap-assisted tunneling. It is found that di€erent VG results in interface-state distribution with different energy-level edges in the forbidden gap. This phenomenon gives a new insight on the mechanism of interface-state generation: the energy release when holes are neutralized by electrons during stressing, depends on the energy the carriers obtain from the stress field which is related to VG and VD. Smaller released energy prefers to break those bonds with lower binding energy (e.g. strained Si-O bonds) and thus creates shallow interface states and vice versa. Hence, the effects of these shallow interface states on device reliabilities are a major concern because they would be highly created by the low operating voltage of MOSFETs. In addition, it is suggested that interface traps which are most effective in assisted tunneling are those closest to the mid-gap from the analyses on the barrier height of tunneling.

Performances of gate dielectrics prepared by double-nitridation in NO and N2O are investigated. Stronger oxide/Si interface bonding, less charge trapping and larger charge-to-breakdown are observed for such gate dielectrics than singly NO-nitrided gate dielectric. The physical mechanisms behind the findings are attributed to larger nitrogen peak concentration located almost at the oxide/Si interface and total nitrogen content near the oxide/Si interface of these gate dielectrics.

Oxynitrides were grown on n-and p-type 6H-SiC wet N2O oxidation (bubbling N2O gas through deionized water at 95 C) or dry N2O oxidation followed by wet N2O oxidation. Their oxide/SiC interfaces were investigated for fresh and stressed devices. It was found that both processes improve p-SiC/oxide deteriorate n-SiC/oxide interface properties when compared to dry N2O oxidation alone. The involved mechanism could be enhanced removal of unwanted carbon compounds near the interface due to the wet ambient, and hence a reduction of donor-like interface states for the p-type devices. As for the n-type devices, incorporation of hydrogen-related species near the interface under wet ambient increases acceptor-like interface states. In summary, the wet N2O oxidation can be used for providing comparable reliability for n-and p-SiC MOS devices, and especially obtaining high-quality oxide-SiC interface in p-type MOS devices.