Application specific on-chip network is a promising direction for Networks on Chips (NoCs) to solve the interconnection challenges that Systems on Chips (SoCs) will encounter in the billion-transistor age. This paper presents a novel design methodology named On-Chip Network Evolution, which helps developing an on-chip network rapidly according to a specific application. To explore the network design space more efficiently, a new description language-NetC is introduced, which is a group of syntaxes that can be translated into SystemC programs.

This paper presents FSimGEO, an efficient test generation method for path delay fault test using Fault Simulation and Genetic Optimization. A parallel-vector fault simulator is introduced first, which can simulate several test vector pairs at the same time through introducing a four-valued logic and the Path Status Graph (PSG) of the circuit structure. After this, a special genetic optimization algorithm is used to direct the process of searching and to optimize test sets generated. We have given the fitness function and genetic operators that affect the optimizing efficiency of Genetic Algorithm (GA) in detail. Experiment results have showed that the number of path tested by FSimGEO is about 3.5 times by latter one.

本文主要介绍在本世纪初期微系统芯片在设计方法和测试方法方面所面临的竞争和挑战，可以在哪些方面展开课题的研究。

针对VLSI系统芯片（SoC）级设计中存在的故障模拟和故障估计问题，从系统级行为算法入手，对系统芯片级中故障进行模块划分，抽取了故障模块模型MUS，提出了系统级故障模型和算法，设计并给出了系统芯片级故障模拟系统SysFsim，该系统由系统级组合故障模拟器Hsim 和时序故障模拟器Bsim 构成。经过实验证实，提出的VLSI系统层模拟算法和系统对故障模拟所达到的故障覆盖率（η/%）、占用CPU时间（t/s）和存储量方面都较由门级所用故障模拟算法和系统有较大的改善，HSIM 和BSIM 在系统级对标准电路进行故障模拟所达故障覆盖率分别为94.3%和95.0%。在加入先期研制的PLA/ROM故障测试生成算法和环境TH_TE100，还可实现100输入和100输出的PLA或ROM的故障模拟和测试生成。

差分功耗分析是一种针对密码芯片的攻击手段，它通过分析功耗信息提取芯片密钥。功耗平衡的实现方法可以提供抗功耗攻击的加密硬件。本文介绍了一种由功耗平衡模块组成的延时不敏感（DI）超前进位加法器，这些功耗平衡模块的工作功耗与输入数据无关。本设计的特点是在晶体管级进行功耗平衡。文中给出了功耗平衡模块和普通模块的功耗差分，对比显示电路改进后的模块更安全。