差分功耗分析是一种针对密码芯片的攻击手段，它通过分析功耗信息提取芯片密钥。功耗平衡的实现方法可以提供抗功耗攻击的加密硬件。本文介绍了一种由功耗平衡模块组成的延时不敏感（DI）超前进位加法器，这些功耗平衡模块的工作功耗与输入数据无关。本设计的特点是在晶体管级进行功耗平衡。文中给出了功耗平衡模块和普通模块的功耗差分，对比显示电路改进后的模块更安全。

本文介绍了一种集成电路芯片瞬时功率测量-采集-分析系统。这是一种基于普通设备搭建的软硬件结合的测试系统。文中详细介绍了系统的测量方案，以及系统组成和各部分的功能与实现，并给出了需要注意的细节。

This paper describes a new scalable architecture of Montgomery modular multiplier (MMM) using our improved FIOS algorithm. This algorithm and architecture can manipulate operands of any precision (bit length) in dual field (prime field and binary field) and has the advantage of using relatively smaller latency (clock cycles) to complete one modular multiplication. Our architecture is reusable and has high performance with respect to latency, timing, area, etc.

This paper presents a novel architecture of register files that combines the local register files and the global register file for clustered VLIW (Very Long Instruction Word) processors. The communication between function units through global register file will be more efficient. The concept of associate register is introduced for this architecture. This makes it possible to write a result to two destination registers in one operation, which can efficiently speed up the software pipelining.

In this paper, a new systematic method to synthesize the low-complexity and low-power realization of high-order FIR filters in VLSI was proposed. First, FIR filter was reprensented in graph, and the coefficients were reordered to generate a optimal realization structure using minimum spanning tree algorithm. Then the common subexpressions in the multiple constant multiplier array were extracted and reused to get further reduction in computational complexity. Finally, we gave some results of proposed method to demonstrate its effectiveness and high efficiency in synthesis of FIR filter in VLSI.We have achieved 36% reduction in implementation complexity without performance degradation.