本文介绍了一种集成电路芯片瞬时功率测量-采集-分析系统。这是一种基于普通设备搭建的软硬件结合的测试系统。文中详细介绍了系统的测量方案，以及系统组成和各部分的功能与实现，并给出了需要注意的细节。

集成电路的工作功率与其处理数据间的相关性是“功耗分析攻击”[1]的物理基础。本文分析了CMOS电路的状态和输入数据影响电路功耗的各种机制——其中考虑了静态电流、信号变化速率等因素，给出了一个动态CMOS逻辑门瞬态电流与数据间的相关关系模型。并由它推算基本逻辑门工作电流的信息量，与仿真结果进行了对比说明。本文主要结论包括：N型动态电路具有更高的安全性；次开启电流、短路电流同样可以泄漏数据信息；电源电流还可能泄漏上次运算和前级电路所处理数据的部分信息等。

差分功耗分析是一种针对密码芯片的攻击手段，它通过分析功耗信息提取芯片密钥。功耗平衡的实现方法可以提供抗功耗攻击的加密硬件。本文介绍了一种由功耗平衡模块组成的延时不敏感（DI）超前进位加法器，这些功耗平衡模块的工作功耗与输入数据无关。本设计的特点是在晶体管级进行功耗平衡。文中给出了功耗平衡模块和普通模块的功耗差分，对比显示电路改进后的模块更安全。

This paper describes a new scalable architecture of Montgomery modular multiplier (MMM) using our improved FIOS algorithm. This algorithm and architecture can manipulate operands of any precision (bit length) in dual field (prime field and binary field) and has the advantage of using relatively smaller latency (clock cycles) to complete one modular multiplication. Our architecture is reusable and has high performance with respect to latency, timing, area, etc.

Application specific on-chip network is a promising direction for Networks on Chips (NoCs) to solve the interconnection challenges that Systems on Chips (SoCs) will encounter in the billion-transistor age. This paper presents a novel design methodology named On-Chip Network Evolution, which helps developing an on-chip network rapidly according to a specific application. To explore the network design space more efficiently, a new description language-NetC is introduced, which is a group of syntaxes that can be translated into SystemC programs.