A 1:4 static frequency divider has been designed and realized in a 0.35-micron standard CMOS technology. The chip consists of two identical 1:2 divider cells, which are based on SCL (Source Coupled Logic) flip-flops. By revising the traditional topology of SCL flip-flop, we get a divider with better perforrrmances. Mesurement results show that the whole chip achieves the frequency division at more than 6GHz. Each 1:2 divider consumes llmW from a 3.3V supply. The divider can be used in RF and Optic-fiber Transceivers and othex high-speed systems.

本文介绍东南大学射频与光电集成电路研究完全利用国内资源，开发拥用自主知识产权的光纤用户专用集成电路芯片，产、学、研相结合的初步实践。

An integrated laser/modulator driver for high-speed optical fiber communication systems has been developed. The integrated circuit was fabricated in a 0.2um gate length AIGaAs/lnGaAs/GaAs pseudomosphin high eleetron mobility transistors (pHEMTs) technology with thin film resistors, metal-insulator-metal (MIM) capacitors and spiral induetors. Its large signal bandwidth is over 12 GHz. The eye diagrams were measured at bit rate up to 12Gb/s with an output voltage swing of 3.4 Vp-p at single end of output. With measured charaetaristies we estimate that the driver IC can operate at bit rate of higher than 24 Gb/s. The power consumption is less than 1.8W using a single supply voltage of-4.5V.

本文提出了一种可编程复接方法和结构。通过对编程端的设置可得到2:1、3:1、4:1及5:1的复接模式。该方法鲁棒性强、应用范围广。其组合可实现除包含大于6的质数之外所有路数的复接，解决了光纤通信系统中不同复接模式对应不同复接结构的问题通过理论推导。本文着重分析了器件延时和时钟相位对芯片工作的影响。并指出了解决途径。基于本方法和结构的全定制单片寨成电路采用0.35μm CMOS工艺制造，芯片面积为24.19mm2，实现了申行输出最高效据速率为1.62Gbps的10:1复接。在1.25Gbps标准速率，工作电压3.3V，负载为50Ω的条件下，功耗仅为74.84mW。输出电压峰-峰值可达到2.42V，占空比为49%．抖动为35ps rms。测试结果表明芯片在复接性能、速度、功耗和面积优化方面的先进性，可满足不同吉比特率通信系统的要求。具有广泛应用和产业化前景。

介绍了甚短距离（VSR）光传输技术及其发展趋势，对VSR光传精实现中的一些关键技术进行简要论述以12信道并行垂直腔面激光器（VCSEL）光发射及接收模块为倒，讨论发射模块中12通道并行VCSEL阵列驱动电路及接收模块中前置放大器和限幅放大器集成电路的实现。测试结果表明，驱动电路每信道精出调制电流超过30mA。 电路速度高达每通道3.125Gbit/s。前置放大器和限幅放大器工作速度达2.5Gbit/s