本文讨论了景点生活上注入下晶体管的IC-VBE特性的各种因素，作者发现发射结势区准费米能降落的影响对于解释实验中发现的n-d（Vas/Vr）/d in Tc<1的情况是重要的，文中也给出了精确测量集成晶体管对的n*值的差分方法。

求出了平面工艺所得圆柱边界的突变结的电位分布的解析解，它由若干项拉普斯议程的解和一项泊松方程的解组成，此解不象通常的圆柱对称解；在圆柱与平面的交界部分不存在不匹配，计算了击穿电压，其值略高于过去常用平面结击穿电压值，且用一个简单表示。

半导体三极管在鲍和工作时，其等效电路可以用一极管及一个由集电极基极构成的二级管联成的电路表示出来，其中三极管在有源区工作，而二极管在正向温压下工作。这样的等效电路具有比较明显的物理意义。利用这个电路来求漂移管在一个共基电路中冲工作下的储存时间。解出非平衡少数流子的连惯性方程。求出二极管p-n结附近非平衡少数流于密度的稳定分量及态分量，从而得到决定储存时间的方程。计算结果表明，储存时间与基极区域集电区塸中非平衡流子的寿命及表面复合速度有关。减少寿命及增加表面复合速度就可以储存时间。

A theory of the switching respinse of the CBMOST (OR COOLMOST, or Super Junction device) is proposed based on the physical nd geo-metracal parameters inherent in the voltage sustaining structure. It is proven that the salient feature of such a device is that the storage time in turn-off process is a little longe than the conventional power Most due to its heavier doping. Explanation for the fast turn-on Process DESPITE OF Having an oppositely doped region inside the voltage sustaining layer is also given. It is also shown that if p-(or n-) regions in the CB-sturcture are not directly contacted to the n+(or p+) drain region. Then device is a normally-on one. Measures are proposed for the real device to be not normally-on.

The novel structure for surface voltage sustaining region makes power (or high-voltage) devices capable to implement on conventional CMOS or BiCMOS ICs without demanding additional process. The electrical performances of this king of power devices are much better than made by BCD techniques. Different kind of devices using for both low-side and high-side can be made.