-
50浏览
-
0点赞
-
0收藏
-
0分享
-
97下载
-
0评论
-
引用
期刊论文
A 3.125-Gb/s CMOS Word Alignment Demultiplexer for Serial Data Communications
,-0001,():
A cascaded 1:10 demuldplexer with comma detection and word alignment has been developed and fabricated using a 0.25gin CMO$ technology. It operates at half the clock frequency of the input data and uses a word alignment clock divider to ensure the parallel data output at the word boundary. Tested on wafer, the chip can operate from IGb/s to 3,125Gb/s to meet various specifications, The measured peak-peak voltage is above 700mV based on 50 load and the phase jitter is l lps rms at the 3.125-Gb/s standard input bit rate. The power consumption is 234mW with a 3.3V supply and the chip area 1.3mm2.
【免责声明】以下全部内容由[王志功]上传于[2005年03月08日 00时03分55秒],版权归原创者所有。本文仅代表作者本人观点,与本网站无关。本网站对文中陈述、观点判断保持中立,不对所包含内容的准确性、可靠性或完整性提供任何明示或暗示的保证。请读者仅作参考,并请自行承担全部责任。
本学者其他成果
同领域成果