针对VLSI系统芯片（SoC）级设计中存在的故障模拟和故障估计问题，从系统级行为算法入手，对系统芯片级中故障进行模块划分，抽取了故障模块模型MUS，提出了系统级故障模型和算法，设计并给出了系统芯片级故障模拟系统SysFsim，该系统由系统级组合故障模拟器Hsim 和时序故障模拟器Bsim 构成。经过实验证实，提出的VLSI系统层模拟算法和系统对故障模拟所达到的故障覆盖率（η/%）、占用CPU时间（t/s）和存储量方面都较由门级所用故障模拟算法和系统有较大的改善，HSIM 和BSIM 在系统级对标准电路进行故障模拟所达故障覆盖率分别为94.3%和95.0%。在加入先期研制的PLA/ROM故障测试生成算法和环境TH_TE100，还可实现100输入和100输出的PLA或ROM的故障模拟和测试生成。

Application specific on-chip network is a promising direction for Networks on Chips (NoCs) to solve the interconnection challenges that Systems on Chips (SoCs) will encounter in the billion-transistor age. This paper presents a novel design methodology named On-Chip Network Evolution, which helps developing an on-chip network rapidly according to a specific application. To explore the network design space more efficiently, a new description language-NetC is introduced, which is a group of syntaxes that can be translated into SystemC programs.

本文提出了一种新的流水线处理器的功能验证方法。这种方法的主要思想是通过验证流水线处理器中所有寄存器的功能来验证处理器的功能。流水线处理器绝大部分是由同步电路组成的。同步电路的状态完全由寄存器的状态决定。因此如果能够保证每个寄存器功能正确就可以保证整个同步电路功能正确。对于流水线处理器来说，寄存器状态的变迁是由处理器的原始输入和寄存器本身状态决定的。原始输入包括控制信号如复位信号和数据输入如指令输入。如果把对每个寄存器的赋值操作转换成对控制信号和数据输入的操作，那么就可以生成一个验证序列，这个序列包括每个时钟周期控制信号和数据输入的值。有了这个序列就可以把目标设计和参考模型进行结果比较，从而验证目标设计功能是否正确。同时这种方法便于调试。

In this paper, a new systematic method to synthesize the low-complexity and low-power realization of high-order FIR filters in VLSI was proposed. First, FIR filter was reprensented in graph, and the coefficients were reordered to generate a optimal realization structure using minimum spanning tree algorithm. Then the common subexpressions in the multiple constant multiplier array were extracted and reused to get further reduction in computational complexity. Finally, we gave some results of proposed method to demonstrate its effectiveness and high efficiency in synthesis of FIR filter in VLSI.We have achieved 36% reduction in implementation complexity without performance degradation.

In this paper, a novel algorithm called logic depth oriented (LDO) common subexpression elimination (CSE) is proposed. In order to avoid the increase of logic depth in circuit structure that may be caused by the application of some other CSE techniques, the process of common subexpressions eliminating of this algorithm is logic depth oriented and the realization of logic operators reuse will not lead to the increase of logic depth. A complete description of the LDO algorithm and the comparisons with several popular CSE algorithms are presented in this paper. Results of comparisons show that using this algorithm can realize the logic operators reuse efficiently, while the logic depth in circuit structure will maintain optimal. Application of this method in the multiplierless VLSI implementation of high-speed FIR filters or some other multiple constant multiplication (MCM) problems will contribute to the high performances in several aspects such as area, speed and power dissipation.