针对VLSI系统芯片（SoC）级设计中存在的故障模拟和故障估计问题，从系统级行为算法入手，对系统芯片级中故障进行模块划分，抽取了故障模块模型MUS，提出了系统级故障模型和算法，设计并给出了系统芯片级故障模拟系统SysFsim，该系统由系统级组合故障模拟器Hsim 和时序故障模拟器Bsim 构成。经过实验证实，提出的VLSI系统层模拟算法和系统对故障模拟所达到的故障覆盖率（η/%）、占用CPU时间（t/s）和存储量方面都较由门级所用故障模拟算法和系统有较大的改善，HSIM 和BSIM 在系统级对标准电路进行故障模拟所达故障覆盖率分别为94.3%和95.0%。在加入先期研制的PLA/ROM故障测试生成算法和环境TH_TE100，还可实现100输入和100输出的PLA或ROM的故障模拟和测试生成。

In this article, the estimation of Harmonic to Noise Ratio (HNR) in transmitted sound signals with wavelet transform was proposed. When subjects phonate sustained vowels in breathy, falsetto, leakage and pressed mode in normal loudness, the HNR in human voice and transmitted sound signals was estimated and compared. The results indicated that the NHR in transmitted sound signals could accurately image vocal folds vibration modes and characteristics. It would be one of useful measurements for clinical laryngeal disease diagnosis.

This paper presents FSimGEO, an efficient test generation method for path delay fault test using Fault Simulation and Genetic Optimization. A parallel-vector fault simulator is introduced first, which can simulate several test vector pairs at the same time through introducing a four-valued logic and the Path Status Graph (PSG) of the circuit structure. After this, a special genetic optimization algorithm is used to direct the process of searching and to optimize test sets generated. We have given the fitness function and genetic operators that affect the optimizing efficiency of Genetic Algorithm (GA) in detail. Experiment results have showed that the number of path tested by FSimGEO is about 3.5 times by latter one.

本文介绍了一种用于系统芯片测试的测试方案。该测试方案包括测试外壳，测试访问结构和自定义测试控制器。对于一个指定的SoC，该测试方案采用整数线性规划的方法对测试时间作出优化。实验结果表明，对于ITC'02 测试标准电路，该测试方案是一种有效的系统芯片测试方法。

在集成电路设计中，面积、功耗和可测性是三个最为重要的优化指标。测试成本正随着集成电路规模的不断增大提高，因此在设计中加入可测性设计的考虑已成为共识。基于扫描的可测性设计方法是目前应用最广泛的方法之一。加入扫描结构可以大大提高电路系统的测试性能，但同时也会给系统的面积、性能、功耗等带来一些负面影响。本文提出了一种考虑低功耗因素的可测性设计方法。计算数据显示，与传统扫描设计方法相比，这种方法在改善系统测试功耗方面具有突出的优势。