A new BPSOI (buried layer partial SOI) structure is developed, in which the P-type buried layer is implanted into the P substrate by silicon window underneath the source of the conventional PSOI. The mechanism of breakdown is that the additional electric field produced by P-type buried layer charges modulates surface electric field, which decreases drastically the electric field peaks near the drain and source junctions. Moreover, the on-resistance of BPSOI is decreased as a result of increasing drift region doping due to neutralism of P-type buried layer. The results indicate that the breakdown voltage of BPSOI is increased by 52-58% and the on-resistance is decreased by 45-48% in comparison to conventional PSOI in virtue of 2-D numerical simulations using MEDICI.

In this paper, a novel double RESURF LDMOS with multiple rings in non-uniform drift region is proposed and successfully fabricated. The proposed device maximizes the benefits of the double RESURF technique by optimizes key process and device geometrical parameters in order to achieve the lowest on-resistance with the desired breakdown voltage. In addition, a versatile JFET device is firstly developed. The JFET device cannot only be used as the current detector, but also be used as the internal power supply for SPIC. Besides, it is compatible with Bipolar-CMOS technology, without any additional processes required.

This paper for the first time systematically analyzed the operation mechanism of SiC NPN transistors. Theoretical device figure-of-merits for switching power devices based on the conduction loss and switching loss were developed. The on-state loss and the switching loss of 4.5-kV SiC switching power devices (MOSFET, NPN transistor and GTO thyristor) were then compared by using theoretical and numerical calculations. Special emphasis is placed on comparing the total power loss of the devices at a given current density. Theoretical analyses and simulation results show that GTO thyristors have a large switching loss due to the long current tail at turn-oll, hence restricting its maximum operation frequency. High voltage SiC MOSFETs have a large on-state power dissipation at high current levels due to the resistive nature of the drift region, restricting their applications at high current densities. SiC NPN transistors have a comparable switching loss as that of SiC MOSFETs, but at the same time, SiC NPN transistors have the lowest on-state loss. This study indicates that SiC NPN transistor is the most attractive switching power device at 4.5kV.

This article presents a new MOS gate controlled thyristor-single-gate emitter controlled thyristor (SECT). Its operation is verified by two-dimensional numerical simulations and the operation mechanisms are analyzed. Simulation results obtained on a 2500 V SECT show that the SECT has an excellent high voltage current saturation capability and much wider FBSOA and RBSOA than those of the IGBT and the DC-EST, while at the same time offering lower conduction and switching losses than those of the IGBT.