已为您找到该学者10条结果 成果回收站
【期刊论文】A 3.125-Gb/s CMOS Word Alignment Demultiplexer for Serial Data Communications
王志功, Wen-Hu Zhao, Zhi-Gong Wang, En Zhu
,-0001,():
-1年11月30日
A cascaded 1:10 demuldplexer with comma detection and word alignment has been developed and fabricated using a 0.25gin CMO$ technology. It operates at half the clock frequency of the input data and uses a word alignment clock divider to ensure the parallel data output at the word boundary. Tested on wafer, the chip can operate from IGb/s to 3,125Gb/s to meet various specifications, The measured peak-peak voltage is above 700mV based on 50 load and the phase jitter is l lps rms at the 3.125-Gb/s standard input bit rate. The power consumption is 234mW with a 3.3V supply and the chip area 1.3mm2.
-
50浏览
-
0点赞
-
0收藏
-
0分享
-
97下载
-
0
-
引用
【期刊论文】A 0.35um CMOS 6.1GHz 1:4 Static Frequency Divider
王志功, Lu Jianhua, Wang Zhigong, Chen Haitao, Xie Tingting, Chen Zhiheng, Tian Lei, Dong Yi", Xie Shizhong*
,-0001,():
-1年11月30日
A 1:4 static frequency divider has been designed and realized in a 0.35-micron standard CMOS technology. The chip consists of two identical 1:2 divider cells, which are based on SCL (Source Coupled Logic) flip-flops. By revising the traditional topology of SCL flip-flop, we get a divider with better perforrrmances. Mesurement results show that the whole chip achieves the frequency division at more than 6GHz. Each 1:2 divider consumes llmW from a 3.3V supply. The divider can be used in RF and Optic-fiber Transceivers and othex high-speed systems.
frequency divider,, flip-flop,, CMOS
-
36浏览
-
0点赞
-
0收藏
-
0分享
-
80下载
-
0
-
引用
王志功, 王晓明, 黄(廷頁), 刘欢艳, 乔卢峰, 苗澎
,-0001,():
-1年11月30日
介绍了甚短距离(VSR)光传输技术及其发展趋势,对VSR光传精实现中的一些关键技术进行简要论述以12信道并行垂直腔面激光器(VCSEL)光发射及接收模块为倒,讨论发射模块中12通道并行VCSEL阵列驱动电路及接收模块中前置放大器和限幅放大器集成电路的实现。测试结果表明,驱动电路每信道精出调制电流超过30mA。 电路速度高达每通道3.125Gbit/s。前置放大器和限幅放大器工作速度达2.5Gbit/s
甚短距离, 垂直腔面激光器, 驱动器, 前置放大器, 限幅放大器
-
35浏览
-
0点赞
-
0收藏
-
0分享
-
135下载
-
0
-
引用
【期刊论文】1.25-Gb/s 0.25-um CMOS Clock Recovery Based on Phase- and Frequency- Locked Loop
王志功, Yah Hu and Zhi-Gong Wang
,-0001,():
-1年11月30日
A 1.25-Gb/s clock recovery (CR) circuit for Very Short Reach (VSR) OC-192/STM-64 parallel optics Interface Is realized based on a phase-and frequency-locked loop. The test CR IC achieves awide locking range from 1.03GHz to 1.42GHz, a small rms Jitter of 4.62 ps (0.00368 UI) for a pseudorandom bit sequence (PRBS) length of 231-1. Tbe DC consumption Is 132 roW,
-
35浏览
-
0点赞
-
0收藏
-
0分享
-
41下载
-
0
-
引用
【期刊论文】24Gb/s Laser/Modulator Driver IC Using 0.2um Gate Length PHEMTs*
王志功, Ting Huang, Zhigong Wang, En Zhu, Xiaoming Wang and Mingzhen Xiong
,-0001,():
-1年11月30日
An integrated laser/modulator driver for high-speed optical fiber communication systems has been developed. The integrated circuit was fabricated in a 0.2um gate length AIGaAs/lnGaAs/GaAs pseudomosphin high eleetron mobility transistors (pHEMTs) technology with thin film resistors, metal-insulator-metal (MIM) capacitors and spiral induetors. Its large signal bandwidth is over 12 GHz. The eye diagrams were measured at bit rate up to 12Gb/s with an output voltage swing of 3.4 Vp-p at single end of output. With measured charaetaristies we estimate that the driver IC can operate at bit rate of higher than 24 Gb/s. The power consumption is less than 1.8W using a single supply voltage of-4.5V.
-
27浏览
-
0点赞
-
0收藏
-
0分享
-
99下载
-
0
-
引用